Senior Mixed-Signal Intellectual Property Register Transfer Level Design Engineer

2 days ago

Hillsboro, United States Microsoft Corporation Full time
Job Summary

We are seeking a highly skilled Senior Mixed-Signal Intellectual Property Register Transfer Level (IP RTL) Design Engineer to join our team at Microsoft Corporation. As a key member of our Silicon Manufacturing and Package Engineering team, you will play a critical role in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale, and sustainability related to Microsoft cloud hardware.

Responsibilities
  • Specify and micro-architect digital blocks and collaborate with analog design teams to define digital/analog interfaces.
  • Write RTL code for blocks based on architectural specifications.
  • Participate in design verification and bring-up of such blocks by writing substantial assertions, debugging code, and interacting with the design verification team.
  • Define, create, and maintain project documentation, including design documents with analysis reports.
  • Develop micro-architectural understanding of mixed-signal systems on IP and SOC level.
  • Describe the power intent of the design through UPF.
  • Perform design quality checks such as Lint, CDC, RDC, Low Power Intent, Synthesis, Logic Equivalence.
  • Understand Dataflow and Clocking requirements and drive solutions for timing critical paths.
  • Automate tasks using scripting for efficiency.
  • Delight customers by providing high-quality functional blocks on schedule and with professional integrity.
  • Collaborate with cross-functional team members with respect and a One Microsoft mentality to establish synergies.
  • Challenge the status quo with a growth mindset.
Qualifications

We are looking for a highly skilled and experienced engineer with a strong background in digital and analog design. The ideal candidate will have:

  • 7+ years of related technical engineering experience.
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience.
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience.
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 5+ years of experience with front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).
  • 5+ years of experience with Verilog/System Verilog coding constructs.
  • 3+ years of experience in Static Timing Analysis and timing signoff fundamentals.
Additional Requirements

The ideal candidate will also have the ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.

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