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Senior Digital Design Engineer with RTL Experience
1 month ago
About CV Library:
CV Library is a leading platform for job seekers and employers to connect. We are committed to providing high-quality job listings that cater to various industries and skill sets.
Job Title: Senior Digital Design Engineer with RTL Experience
Estimated Salary: £70,000 - £100,000 per annum (dependent on location and experience)
Job Description:
We are seeking an experienced Senior Digital Design Engineer with expertise in Register-Transfer Level (RTL) design to join our team. The successful candidate will be responsible for designing and implementing complex digital circuits using Verilog or VHDL. The role requires strong knowledge of ASIC design flows, including synthesis, place and route, and static timing analysis.
The ideal candidate will have a proven track record of delivering high-quality designs within tight deadlines. They will also have excellent communication skills and be able to collaborate effectively with cross-functional teams, including architecture, hardware, verification, and physical design.
Key Responsibilities:
- Design and implement complex digital circuits using Verilog or VHDL
- Develop and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements
- Collaborate with architecture and hardware teams to understand requirements
- Work with verification and physical design teams to achieve high-quality design and successful tape-out
- Participate in silicon bring-up for features owned
- Contribute to cross-functional teams to solve client problems across multiple functional areas in development of required features
- Implement automation to increase design team efficiency
Required Skills and Qualifications:
- 5-6+ years' experience in ASIC design
- Proven track record of delivering high-quality designs within tight deadlines
- Strong knowledge of ASIC design flows, including synthesis, place and route, and static timing analysis
- Experience with Arm architecture and APB, AXI, CHI protocols
- Experience with synthesis, static timing analysis & optimizations
- Ability to develop clear and concise engineering documentation
- Strong verbal and written communication skills
Benefits:
- Competitive salary (£70,000 - £100,000 per annum)
- Opportunity to work on exciting projects with a leading company
- Chance to develop skills and expertise in a dynamic and supportive environment
Others:
Please note that this is an estimated salary range, and actual salaries may vary based on location and experience. If you are interested in this opportunity, please submit your application for further consideration.
