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Senior Physical Design Engineer, Top Level

2 months ago

Beaverton, Oregon, United States Apple Full time
Job Summary

We are seeking a highly skilled Senior Physical Design Engineer to join our team at Apple. As a key member of our design team, you will be responsible for implementing complete chip design from netlist to tapeout.

Key Responsibilities
  • Work with the Front-End (FE) team to understand chip architecture and drive physical aspects early in the design cycle.
  • Collaborate with the physical design team to drive methodologies and best practices to streamline physical design work, develop guidelines and checklists, drive execution, and track progress.
  • Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, and understand dependencies between different domains like top, Static Timing Analysis (STA), block place and route.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
Requirements
  • Minimum Bachelor's degree and 10+ years of relevant industry experience.
  • Familiarity with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
  • Experience with typical System-on-Chip (SoC) issues such as multiple voltage and clock domains, Electrostatic Discharge (ESD) strategies, mixed signal block integration, and package interactions.
  • Experience integrating IP from both internal and external vendors and ability to specify and drive IP requirements in the physical domain is required.
  • Detailed understanding of database management issues is required.
  • From a CAD tool perspective, experience with floorplanning tools, Place and Route (P&R) flows, global timing verification, and physical design verification flows is required.
Preferred Qualifications
  • Familiarity with a hierarchical design approach, top-down design, budgeting, timing, and physical convergence.
  • Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 7nm technologies.
  • Familiarity with various process-related design issues including Design for Yield and Manufacturability, multi-Vt strategies, and thermal management.