Post Silicon Validation Engineer

4 days ago


Santa Clara, California, United States L&T Technology Services Full time

Job Summary

L&T Technology Services is seeking a highly skilled Post Silicon Validation Engineer to join our team. As a Post Silicon Validation Engineer, you will be responsible for validating the functionality and performance of silicon devices.

Key Responsibilities

  • Validate the functionality and performance of silicon devices, including PCIe, Ethernet, and DDR interfaces.
  • Develop and execute test plans to ensure compliance with industry standards and customer requirements.
  • Collaborate with design teams to debug problems and performance issues, and report results to design teams.
  • Support customer silicon bring-ups and post-silicon queries of IP, and help to debug customer issues with samples.
  • Execute special test requests from design teams or customers to measure specific parameters or root cause issues.
  • Develop and maintain test scripts using Python, and analyze data to identify trends and areas for improvement.
  • Work with cross-functional teams to identify and prioritize test requirements, and develop test plans to meet those requirements.
  • Stay up-to-date with industry trends and advancements in silicon validation, and apply that knowledge to improve test methodologies and tools.

Requirements

  • 8+ years of experience in post-silicon validation, with expertise in PCIe, Ethernet, and DDR interfaces.
  • Strong understanding of JEDEC, PCIe, and Ethernet standards.
  • Experience with high-speed scopes, probes, spectrum analyzers, and BERTs.
  • Excellent problem-solving skills, with the ability to debug complex issues and develop creative solutions.
  • Strong communication and collaboration skills, with the ability to work effectively with cross-functional teams.
  • Proficiency in Python programming, with experience in test scripting and data analysis.

Preferred Qualifications

  • Experience with test cards for PCIe and Ethernet.
  • Knowledge of lab equipment and measurement techniques for high-speed interfaces.
  • Experience with defect management and repository management systems.
  • Strong understanding of hardware debug flow and silicon architecture.


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