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Camden, New Jersey, United States Bestinfo Systems LLC Full time{"title": "Senior ASIC/FPGA Design Engineer", "content": "Job SummaryWe are seeking a highly skilled Senior ASIC/FPGA Design Engineer to join our team at Bestinfo Systems LLC. As a key member of our engineering staff, you will be responsible for designing and implementing high-speed crypto architectures on ASICs and FPGAs.Key Responsibilities:Derive...
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FPGA/ASIC Design Specialist
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Camden, New Jersey, United States Aloden, Inc. Full timeAbout the RoleWe are seeking a highly skilled FPGA/ASIC Design Engineer to join our team at Aloden, Inc. as a key contributor to our defense and aerospace projects.Key ResponsibilitiesDesign, develop, and implement complex algorithms on FPGAs and ASICs for defense and aerospace applications.Utilize VHDL for hardware description and implementation.Conduct...
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FPGA Design Engineer
1 month ago
The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, and verification/validation of complex FPGAs and/or ASICs systems. This is a key role in the organization to ensure robust quality and delivery of Communication products for National Security.
Key Responsibilities:- Develop architectures for implementation of high-throughput complex designs involving Cryptographic Algorithms (VHDL) with high-speed protocols- NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs and/or ASICs.
- Write and debug tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also write and debug software-based SW driven validation on SOC evaluation boards.
- Utilize state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), and Catapult (HLS).
- At least 3 years' experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs.
- Bachelor of Science in Electrical or Computer Engineering or Master of Science in Electrical or Computer Engineering preferred.
- Proficiency in VHDL and FPGA design/debug Xilinx FPGA / Vivado.
- Excellent Analytical/Debug skills.
- Active Secret Clearance required.
- High Level Synthesis (HLS) with Vivado.
- Embedded SW C++ (OOP) and System Verilog Assertions (SVA).
- Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet).
About Actalent:
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation, and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia, and Europe, Actalent serves many of the Fortune 500.
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