Senior Verification Engineer
18 hours ago
Acceler8 Talent is seeking an experienced Design Verification Engineer to join a high-performing team in San Francisco, contributing to the creation of best-in-class silicon for high-performance and sustainable Generative AI.
This company, founded by industry veterans, is pushing the boundaries of what Large Language Models can accomplish. With a team comprised of talent and passion, they're driving innovation in the field.
As the Design Verification Engineer, you'll be responsible for developing and executing verification methodologies across blocks, subsystems, full chip, and system-level validation. You'll own portions of the verification execution at the subsystem and chip level, creating testbenches and executing progress and verification closures toward various silicon milestones.
This role is ideal for those with:
- Experience driving verification from concept-to-silicon
- Knowledge of scripting languages, including SystemVerilog, Python, and C/C++
- Knowledge of LPDDR/HBM or Ethernet/Mac/PCS/NOC
- Production experience with advanced verification methodologies (UVM, AVB, formal verification, etc.)
- Strong understanding of silicon micro-architecture and design concepts used in high-performance compute, high-speed connectivity, memory management, and related functionalities
- 5+ years working in design verification roles
Familiarity with emulation and prototyping platforms and methodologies, as well as hands-on experience with participation in silicon debugging and bring-up, are pluses.
Base Salary: $200,000 - $300,000 + equity + benefits
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