Senior Verification Engineer

4 days ago


Mountain View, California, United States Acceler8 Talent Full time
Design Verification Engineer

This innovative startup in Mountain View, CA is revolutionizing the computing landscape with its cutting-edge GenAI platform. Founded by industry pioneers, they are pushing the boundaries of large language models, graphics processing units, and machine-learning models to make AI more accessible, efficient, and cost-effective.

We are seeking a seasoned Principal-level Design Verification Engineer to join their team as they create industry-leading silicon for high-performance and sustainable GenAI.

This is a full-time hybrid role (Tues-Thurs) in the Mountain View, CA office.

Key Responsibilities
  • Develop and enhance their verification methodology by creating scalable solutions for blocks, subsystems, full-chip, and system-level validation.
  • Take ownership of specific portions of verification execution at the subsystem and chip levels, including the creation of testbenches, tests, and related artifacts to ensure both structural and functional coverage closure.
  • Lead planning and conduct intermediate and sign-off reviews of verification test plans, monitor execution progress, and achieve verification closure for various silicon milestones such as design freeze and tapeout.
Requirements
  • Proven experience driving verification from an architecture and/or design specification through to production silicon.
  • Proficiency in SystemVerilog, Python, C/C++, Bluespec, and similar scripting and programming languages used for verification and silicon modeling.
  • Hands-on experience with advanced verification methodologies such as UVM and assertion-based verification (ABV); a strong familiarity with both formal and simulated verification techniques is essential.
  • Demonstrated experience in creating portable tests and drivers for verification, applicable to silicon validation and post-silicon debug.
  • Deep understanding of silicon micro-architecture and design concepts, particularly in high-performance computing (CPUs, GPUs, accelerators), high-speed connectivity, memory management, and related functionalities.
  • Familiarity with emulation and prototyping platforms and methodologies is advantageous.
  • Practical experience in silicon debug and bring-up processes is a plus.

All candidates must be authorized to work in the United States and work from their offices in Mountain View Tuesdays-Thursdays.



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