Principal Verification Engineer

12 hours ago


Dallas, Texas, United States Glow Networks Full time
Job Summary

The Principal Verification Engineer will be responsible for designing and implementing verification environments using System-Verilog and UVM IPs for IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.

They will develop test plans and coverage metrics, create scripts to automate verification processes, perform failure analysis of simulations, and collaborate with design engineers to resolve issues.

Responsibilities
  • Design and implement verification environments using System-Verilog and UVM IPs for IPs and SoCs.
  • Develop test plans and coverage metrics, and write block and chip-level tests based on specifications.
  • Utilize PERL/Python scripts to automate verification processes and debug.
  • Conduct failure analysis of Register Transfer Level and Gate simulations, collaborating with design engineers for resolution.
  • Work with architects to define simulation use-case scenarios.
Requirements
  • 7+ years of experience in presilicon design verification.
  • Proficiency in Cshell scripting, Verilog-HDL, and System Verilog.
  • Strong knowledge in SV Assertions, UVM/OVM, and functional code coverage.
  • Experience with advanced peripheral bus Verification IPs (e.g., GPIO, UART, SPI, SW, JTAG, I2C).
  • Proficient with Cadence tools like NC Verilog, NCSIM, and Simvision. Experience with linting tools such as Spyglass is beneficial.
  • Independent, self-motivated, with excellent analytical and communication skills.


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