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Design Verification Engineer
2 months ago
G-Research is a leading quantitative research and technology firm, seeking a highly skilled Design Verification Engineer to join our world-class Hardware Engineering function.
Key Responsibilities- Develop and maintain complex verification environments using industry-standard methodologies, such as UVM, SV, and C++.
- Design and implement System Verilog based VMM/UVM test bench environments, assertion and functional coverage verification environments, and co-simulation environments to verify between C/C++ models and RTL modules.
- Write test plans, create test bench specifications, and analyze code coverage plans to ensure efficient and effective verification.
- Implement constrained-random sequences, agents, and environments using the UVM methodology.
- Debug failing simulations to RTL level, identifying and resolving issues to ensure successful verification.
- Extensive experience in large FPGA and ASIC design, with a strong understanding of industry-standard interfaces, such as Avalon and AXI.
- Proficient in programming languages, including Python and C/C++.
- Experience with industry-standard build tools, including version control.
- Knowledge of QuestaSim environment and Fintech background a plus.
- Market-leading compensation and annual discretionary bonus.
- Lunch provided in the office.
- Informal dress code and excellent work/life balance.
- Excellent paid time off allowance of 25 days.
- Sick days, military leave, and family and medical leave.
- Generous 401(k) plan.
- 16-weeks' fully paid parental leave.
- Medical and Prescription, Dental, and Vision insurance.
- Life and Accidental Death & Dismemberment (AD&D) insurance.
- Employee Assistance and Wellness programs.
- Generous relocation allowance and support.
- Great selection of office snacks, and hot and cold drinks.
- On-site gym and car parking.
