ASIC Design Engineer Intern
4 weeks ago
At Ambarella, we are seeking a highly skilled ASIC Design Engineer Intern to join our team. As a key member of our design team, you will be responsible for designing and implementing video compression logic, image processing logic, vector processing, and neural network accelerator logics, as well as processor cores, in Verilog and System Verilog.
Key Responsibilities:- Design and implement video compression logic, image processing logic, vector processing, and neural network accelerator logics, and processor cores in Verilog and System Verilog.
- Develop and implement logic design, implementation, and verification using Verilog, System Verilog, and other required programming and scripting languages.
- Synthesize and optimize RTL for timing, area, and power.
- Develop unit-level and cluster-level test-benches, BFMs, random test generators, functional coverage monitors using System Verilog, UVM, C++, and Perl scripts.
- Develop test plans, random and directed test cases, perform logic verification, and functional coverage analysis.
- Develop front-end methodologies and tool flows.
- Participate in chip bring-up and testing.
- Master's degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.
- Good understanding of computer architecture, logic design, and VLSI design.
- Knowledge of System Verilog, Verilog, and Perl.
- Knowledge of design verification and functional coverage.
- Ability to program scripting languages and write assembly language programs.
- Strong communication skills and a good team player.
- Knowledge of logic synthesis and timing closure is a plus.
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