High-Speed System Architect

3 days ago


San Jose, California, United States Cadence Design Systems Full time

Cadence Design Systems: We are seeking an experienced technical expert to join our team as a Technical Lead for SERDES Validation. This challenging opportunity involves establishing signal and power integrity system budgets, implementing advanced design validation of SERDES training methodologies and flows, and ensuring the operation of interconnects and interfaces of our industry-leading emulation-acceleration system platform.

Key Responsibilities:

  • Develop and maintain in-depth knowledge of high-speed system design principles and SI/PI budgeting methodologies.
  • Lead the development of complex SERDES training algorithms for multi-rack systems with thousands of interconnect links and various channels on boards, systems, copper backplanes, and optical fibers.
  • Define and oversee the development of SI/PI design and validation methodologies for high-speed electrical and optical serial link systems.
  • Collaborate with SI/PI Integrity experts to approve proposed system implementations of link and power budgets.
  • Work with the firmware development team for SOC characterization to develop in-system training and diagnostics.
  • Correlate SERDES link measurement results with SI/PI budgets and document findings.

Estimated Annual Salary: $153,000 - $282,400 based on the location in California.

Benefits:

  • Paid vacation and paid holidays.
  • 401(k) plan with employer match.
  • Employee stock purchase plan.
  • A variety of medical, dental, and vision plan options.


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