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Senior Design Verification Engineering Manager

4 weeks ago

Columbia, South Carolina, United States Cadence Design Systems Full time

Cadence is seeking a highly skilled Verification Engineering Manager to lead our SerDes DV group. The ideal candidate will have a strong background in functional verification fundamentals, verification environment planning & development, and test plan creation.


The role requires the management of a SerDes DV group focusing on MDV verification, including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.


The successful candidate will have prior digital verification experience in serial bus multiprotocol PHY IP's (SerDes IP especially PCIe and other protocols) and strong expertise in Verilog, HVL (SV, e) with UVM/OVM/eRM methodology.


Additional responsibilities include participating in Technical alignment with verification experts in defining verification strategy, architecting verification environment, and representing DV and technically working/leading team interactions with RTL, analog/modeling, PD teams for design verification tasks.


The ideal candidate will have a strong background in functional verification fundamentals, verification environment planning & development, test plan creation, and prior digital verification experience in serial bus multiprotocol PHY IP's (SerDes IP especially PCIe and other protocols).


Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer.