Senior RFIC Design Engineer

3 weeks ago

Irvine, California, United States Apple Full time
Wireless RFIC Design Lead

As a Senior RFIC Design Lead at Apple, you will be responsible for providing RFIC solutions for wireless SoC and driving them to mass production. Your key responsibilities will include:

Key Responsibilities:
  • Lead design of radio transceiver chains including TX, RX, and PLL-LOGen for wireless connectivity products.
  • Drive radio KPI (power, area, performance) to meet product requirements.
  • Work with cross-functional teams to define radio features enabling wireless innovation.
  • Collaborate with RF Systems in block level and high level specifications of the TX and RX line ups and PLL-LOGen.
  • Design of RF and Analog loopbacks for calibration and compensation.
  • Work through Co-Existence scenarios and design to meet the CoEx requirements.
  • Oversee the floorplan layout and verification of the design to ensure a successful tape-out.
  • Closely collaborate with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip.
  • Provide design versus silicon measurements correlation, and compliance with specification for a volume production.
  • Work with the foundry team to understand the capabilities, and limitations of the new technology nodes to achieve the optimum radio performance.

Requirements:
  • Typically requires 10+ years of RF/analog and mixed-signal design experience in cutting-edge RF CMOS design.
  • Direct experience in designing and bringing into mass production of wireless transceivers in deep sub-micron RFCMOS technology.
  • Deep understanding of analog, mixed-signal and RF circuit design.
  • Familiarity with various RF transceiver architectures and their trade-offs, system specifications and ability to work with system architects to translate system requirements into circuit requirements at IC level.
  • Proven capability to work with digital design group for an optimum partition between digital and analog domain.
  • Familiarity with the integration flows and challenges of wireless SoCs.
  • Strong knowledge of desense and able to work closely with board RF/HW/Antenna teams to optimize board/module layouts for desense mitigation.
  • Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS), and similar tools.
  • Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).
  • Extensive experience in Silicon characterization and debug.
  • Ability to drive strong production test/QA methodologies.

Education & Experience:
BS and 10+ years of relevant industry experience. MSEE and PhD is preferred.

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