Senior RFIC Design Engineer

4 weeks ago


Irvine, California, United States Apple Full time
RFIC Design Engineer

We are seeking a highly skilled RFIC Design Engineer to join our team at Apple. As an RFIC Design Engineer, you will be responsible for designing and developing RFIC solutions for wireless SoC and driving them to mass production.

Key Responsibilities:
  • Design radio transceiver chains, including TX, RX, and PLL-LOGen for wireless connectivity products.
  • Drive radio KPI (power, area, performance) to meet product requirements.
  • Work with multi-functional teams to define radio features enabling wireless innovation.
  • Design of RF and Analog loopbacks for calibration and compensation.
  • Work through Co-Existence scenarios and design to meet the CoEx requirements.
  • Be responsible for the floorplan layout and verification of the design to ensure a successful tape-out.
  • Closely collaborate with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip through the productization.
Requirements:
  • BS and 10+ years of relevant industry experience.
  • Shown RF/analog and mixed-signal design experience in groundbreaking RF CMOS design.
  • Strong understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, and other analog impairments.
  • Experience in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS), and similar tools.
  • Direct experience in designing and bringing wireless transceivers into mass production in deep sub-micron RFCMOS technology.
  • Experience should also include understanding DFT and DFM techniques for mass production environments.
Preferred Qualifications:
  • MSEE and PhD plus relevant industry experience.
  • Solid Understanding of the impact of modulation type on radio architecture and requirements.
  • Validated capability to work with digital design group for an optimum partition between digital and analog domains.
  • Familiarity with the integration flows and challenges of wireless SoCs.
  • Good understanding of desense and can work with board RF/HW/Antenna teams to optimize board/module layouts for desense mitigation.
  • Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).
  • Extensive experience in Silicon characterization and debugging.
  • Ability to drive strong production test/QA methodologies.


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