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Senior E/E Engineer

2 months ago

San Francisco, California, United States Capgemini Full time
Job Summary

We are seeking a highly skilled Senior E/E Engineer to lead our DV IP verification team. As a key member of our engineering team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology.

Key Responsibilities
  • Design and develop verification environments for IP and SoC verification
  • Collaborate with cross-functional teams to ensure verification environments meet project requirements
  • Develop and maintain verification scripts and testbenches
  • Identify and troubleshoot verification issues
  • Provide technical guidance and mentorship to junior engineers
Requirements
  • Proficiency in UVM and SystemVerilog
  • Strong knowledge of SV assertions, UVM/OVM, and functional and code coverage analysis
  • Experience with Python scripting and C/C-based reference model debug
  • Strong regression failure and root cause analysis skills
  • Excellent analytical and communication skills
What We Offer
  • Flexible work arrangements
  • Comprehensive healthcare and well-being programs
  • Financial well-being programs, including 401(k) and Employee Share Ownership Plan
  • Paid time off and paid holidays
  • Paid parental leave
  • Family building benefits, including adoption assistance and surrogacy
  • Mentoring, coaching, and learning programs
  • Employee Resource Groups
  • Disaster Relief
About Capgemini Engineering

Capgemini Engineering is a world leader in engineering and R&D services, combining industry knowledge and cutting-edge technologies to support the convergence of the physical and digital worlds. We help clients accelerate their journey towards Intelligent Industry.

With over 55,000 engineer and scientist team members in over 30 countries, we offer a diverse range of services and solutions, leveraging strengths in AI, cloud, and data, combined with deep industry expertise and a partner ecosystem.