Silicon Logic Formal Verification Specialist
5 days ago
Silicon Logic Formal Verification Engineer
Job Summary:Ursus Inc is seeking a skilled Silicon Logic Formal Verification Engineer to join our team. As a key member of our design team, you will be responsible for developing and implementing formal verification solutions for complex digital logic designs.
Responsibilities:- Collaborate with RTL design engineers to identify micro-architecture features for formal micro-architecture specification.
- Develop comprehensive formal verification test plans.
- Prove properties of the design, find design bugs, and work closely with design teams to improve micro-architecture.
- Craft client and creative solutions for verifying complex design micro-architectures.
- Develop and implement reusable and optimized formal models and testbenches.
- Architect correct-by-construction design methodologies for improved formal verification efficiency and productivity.
- Interest in learning and becoming an expert in VLSI and digital logic design and verification techniques.
- Detail-oriented mindset and desire to overcome challenges.
- Formal Method or Formal Verification technologies and abstraction techniques experience is a plus.
- Knowledge in interpreting hardware specifications using assertion-based languages such as SVA.
- Experience in using formal tools and models.
- Proficiency in any scripting language with excellent debugging skills.
- Passionate about developing innovative formal verification solutions.
- Excellent skills in problem-solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
PhD, Master's Degree, or Bachelor's Degree in a technical subject area.
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