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Senior Mixed Signal IC Design Engineer

2 months ago

Goleta, California, United States Raytheon Full time
About the Role

We are seeking a highly skilled Senior Mixed Signal IC Design Engineer to join our team at Raytheon. As a key member of our design team, you will be responsible for the design, development, and verification of read-out ICs (ROICs) for visible and infrared focal plane arrays.

Key Responsibilities
  • Design and develop mixed-signal integrated circuits for image sensors, including analog signal chain, digital timing and image processing, and low-power bit on-chip analog to digital converters.
  • Collaborate with cross-functional teams to deliver on customer requirements, considering efficiencies in strategic investment, cost, schedule, and process adherence.
  • Provide support to the department in areas such as CAD support in CMOS and scripting languages in Linux and Windows environments, as well as layout lead doing chip-level floor planning.
Requirements
  • Typically requires a Bachelor's degree in Science, Technology, Engineering, or Mathematics (STEM) with a minimum of 5 years of prior relevant experience, or a MS degree and minimum of 3 years experience.
  • Experience in mixed-signal full-custom CMOS Integrated Circuit (IC) design at the transistor level.
  • Comprehensive understanding of IC layout flows, methodologies, and layout of digital and analog blocks for use in larger mixed-signal circuits, CAD tools, and statistical design.
  • Knowledge and ability to hand layout critical analog and mixed-signal circuits.
  • U.S. citizenship is required, as only U.S. citizens are authorized to access information under this program/contract.
Preferred Qualifications
  • Experience with high-end Linux-based software design tools for circuit simulation, transistor model extraction, noise analysis, linear design, chip-level floor-planning, IC layout, and automation, and verification.
  • Experience with LVDS transmitters and receivers, low noise and low power amplifiers, ADC design, PLL/Transmitter design, and radiation and cryogenic tolerant design techniques.
  • Analysis and programming experience using MATLAB and at least one computer programming or scripting language (e.g. SKILL, Perl, Tcl, Python, C/C++) in Linux & Windows environments.
  • Modelling experience with System Verilog/Real Modelling/Verilog AMS and coding synthesizable RTL.
  • Experience in installing, maintaining, and troubleshooting of PDK environments for semiconductor foundries. Experience in PDK development.
What We Offer
  • Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX, we value: Trust, Respect, Accountability, Collaboration, and Innovation.

The salary range for this role is $85,000 USD - $179,000 USD. Hired applicants may be eligible for benefits, including medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement.

Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company's performance.

This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.

RTX is An Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age or any other federally protected class.

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