Senior PHY Design Verification Engineer
2 weeks ago
Are you passionate about designing and verifying wireless communication systems? Do you have a strong background in PHY design verification and a keen eye for detail? We're looking for a talented Senior PHY Design Verification Engineer to join our team at Apple.
Key Responsibilities- Design and develop verification plans for PHY subsystems, ensuring they meet the required specifications and standards.
- Build and maintain complex test benches using best-in-class DV methodologies, with a focus on maximum reusability.
- Develop and execute directed and constrained random tests, debug failures, and manage bug tracking to drive closure of issues found.
- Create and analyze block/subsystem level coverage models, adding test cases to increase coverage.
- Support PHY subsystem validation using Palladium and FPGA.
- BS and 3+ years of relevant industry experience.
- Verification experience of wireless/wired communication block/subsystem.
- Excellent knowledge and experience of ASIC verification flows, including test bench development, constrained random testing, and code/functional coverage.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Experience of using Matlab/C reference model and bit-accurate verification a plus.
- Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.
- Proficiency in shell and Perl scripting, Python skills a plus.
- Experience of Palladium/FPGA validation a plus.
- Comprehensive medical and dental coverage.
- Retirement benefits.
- A range of discounted products and free services.
- Reimbursement for certain educational expenses.
- Discretionary bonuses or commission payments.
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