RTL Design Engineer
3 days ago
Job Summary:
We are seeking a highly skilled RTL Design Engineer to join our team at ACL Digital. As an RTL Design Engineer, you will be responsible for delivering high-quality SOC IP designs that meet our stringent quality and performance requirements.
Key Responsibilities:
- Deliver high-quality SOC IP designs: You will work on the development and delivery of SOC IP designs that meet our quality and performance requirements.
- Collaborate with implementation teams: You will work closely with our implementation teams to ensure that your designs meet our timing and area requirements.
- Develop and maintain LINT and CDC flows: You will be responsible for developing and maintaining our LINT and CDC flows to ensure that our designs meet our quality and performance requirements.
- Drive timing debug and closure: You will be responsible for driving timing debug and closure to ensure that our designs meet our timing requirements.
- Develop and debug new features: You will be responsible for developing and debugging new features on our custom memory controller.
- Meet PPA goals: You will be responsible for delivering high-quality designs that meet our PPA goals.
Requirements:
- Knowledge of memory controller: You should have a strong understanding of memory controller design and development.
- Experience in memory technologies: You should have experience in memory technologies such as DDR4/5, LPDDR, and HBM.
- Knowledge of Verilog and scripting: You should have a strong understanding of Verilog and scripting languages.
- Knowledge of STA: You should have a strong understanding of Static Timing Analysis (STA) tools and techniques.
- Knowledge of PHY design: You should have a strong understanding of PHY design and development.
- Energetic and curious: You should be energetic and curious, with a passion for logic design.
- Good written and verbal communication skills: You should have good written and verbal communication skills to effectively communicate with our team.
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