Digital Verification Engineer

2 weeks ago


Palo Alto, California, United States Current Job Openings Full time
Job Summary

The Digital Verification Engineer will play a key role in the verification of innovative digital microarchitecture implementation for FPGAs and ASICs. This is an exciting opportunity to join our Electronic Sub-Systems team and contribute to the development of cutting-edge technology.

Responsibilities
  • Develop and own DV (design verification) testbench, including checkers, monitors, scoreboards, assertions, and functional coverage.
  • Plan and execute test plans and test cases to cover design feature sets, working closely with design engineers to identify important verification scenarios.
  • Collaborate with design teams on failure debug, code coverage, and functional coverage closure.
  • Debug regression failures and identify bug fixes.
  • Create documentation and reports to support the verification process.
Requirements
  • Degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. MS preferred.
  • At least 7 years of industrial experience in related fields.
  • Experience with SystemVerilog and Universal Verification Methodology (UVM).
  • Ability to create constrained-random verification environments using SystemVerilog and UVM.
  • Experience in Silicon bringup and FPGA development.
  • Excellent communication and collaboration skills.

PsiQuantum is an equal opportunity employer and welcomes applications from diverse candidates. We offer a competitive salary range of $125,000-$170,000 USD for this role, depending on qualifications and experience.



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