Principal Digital Design Engineer
2 days ago
This is a fantastic opportunity to join a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. The company is looking for a Principal Digital Design Engineer with over 15 years of experience who will help architect and develop RTL for various products with the area of focus being DDR server-class memory controllers.
Responsibilities- Mentor and lead cross-functional teams to architect, develop and debug digital and mixed signal circuits
- Design various logic & state machines in System Verilog/Verilog RTL
- Develop and debug RTL, using industry-standard simulation and synthesis tools, along with LEC, CDC, Lint, DFT and STA tools
- Provide PPA (Power, Performance, Area) and schedule estimates, as well as design specifications for the RTL
- Coordinate with Verification/AMS design teams to ensure proper operation and functional and code coverage
- Provide floor-planning and support integration of digital & analog circuits at top level
- Work in cooperation with the methodology and CAD teams
- BS or MS in Electrical Engineering, Computer Engineering or equivalent
- Must have 15 years of industry experience with deep understanding in the architecture definition of DDR4/5 server-class memory controllers
- Familiarity with ECC (SECDEC) and CRC
- Knowledge of JEDEC memory standards and CHI/AXI interconnect and bus protocols
- Experience in high speed and low power digital design in advanced deep sub-micron processes
- Understand how to obtain minimum latency and maximum bandwidth
- Understand the tradeoff with command placement and scheduling, can efficiently manage activate and pre-charge commands
- Proficient with System Verilog/Verilog RTL for both behavioral simulations and synthesis
- Proficient with Design Compiler and PrimeTime
- Programming/scripting know-how, e.g. Perl, Tcl and/or Python
- Experience with Linux
- Experience with embedded micro-controllers is beneficial
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