Senior ASIC/FPGA Design Verification Engineer

4 hours ago


El Segundo, California, United States Saxon Global Full time
Job Title: ASIC/FPGA Design Verification Engineer with UVM Expertise

Job Summary:
Saxon Global is seeking a highly skilled ASIC/FPGA Design Verification Engineer with expertise in UVM to join our team. The ideal candidate will have a strong background in design verification and experience with UVM simulation plans, UVC, Score Board, Monitor, and test cases.

Key Responsibilities:
  1. Create UVM simulation plans from design specifications.
  2. Develop or modify UVC, Score Board, Monitor, and test cases.
  3. Verify until functional coverage and code coverage meet project thresholds.
  4. Document results and provide detailed reports.

Requirements:
  • Advanced technical education in engineering, computer science, mathematics, physics, or chemistry.
  • 5 or more years of related work experience or an equivalent combination of technical education and experience.
  • Strong knowledge of UVM and design verification methodologies.
  • Excellent problem-solving and analytical skills.
  • Ability to work in a team environment and collaborate with cross-functional teams.

What We Offer:
  • Competitive salary and benefits package.
  • Opportunities for professional growth and development.
  • Collaborative and dynamic work environment.

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