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Senior ASIC/FPGA Design Engineer

2 months ago

Camden, New Jersey, United States L3 Technologies Full time
Job Title: Lead ASIC/FPGA VHDL Design Engineer

Join our team of experts in designing and developing high-speed crypto ASIC/FPGA products.

About the Role

We are seeking a highly skilled Senior Member of Engineering Staff (SMES) to join our key ASIC/FPGA design team. As a Lead ASIC/FPGA VHDL Design Engineer, you will be responsible for delivering FPGA/ASICs for high-speed crypto applications.

Key Responsibilities
  • Derive engineering specifications from system requirements and develop detailed architecture
  • Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
  • Generate test plans
  • Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
  • Silicon/FPGA bring up, characterization and production ramp/support/collateral
Requirements
  • BSEE, MSEE Preferred
  • 7+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products
  • Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs
  • Proficient with CDC, RDC. Formal EDA
  • Proficient in VHDL is a must
  • Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
  • Strong logic/board debug, and analytical skills
  • Experience with project leadership and EVM
  • Excellent written, verbal, and presentation skills
  • Active SECRET Clearance
Preferred Additional Skills
  • Proficiency in C++ (OOP)
  • Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS
  • Knowledge of PCIe, NVMe, USB protocols
  • Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto)

L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).

This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.