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Senior ASIC/FPGA VHDL Design Engineer with Secret Clearance

1 month ago

Camden, New Jersey, United States Intermedia Group Full time
Job Title: Senior ASIC/FPGA VHDL Design Engineer with Secret Clearance

Job Summary:

We are seeking a highly skilled Senior ASIC/FPGA VHDL Design Engineer with a Secret clearance to join our team. The successful candidate will be responsible for designing and implementing high-speed crypto architectures on ASICs and FPGAs.

Key Responsibilities:

* Derive engineering specifications from system requirements and develop detailed architecture
* Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
* Generate test plans
* Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
* Silicon/FPGA bring up, characterization and production ramp/support/collateral

Requirements:

* Active Secret Clearance
* BSEE
* 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products
* Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs
* Proficient with CDC, RDC. Formal EDA.
* Proficient in VHDL is a must
* Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
* Strong logic/board debug, and analytical skills.
* Experience with project leadership and EVM
* Excellent written, verbal, and presentation skills.

Preferred Skills:

* Proficiency in C++ (OOP)
* Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
* Knowledge of PCIe, NVMe, USB protocols.
* Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).

How to Apply:

If you are interested in this opportunity, please submit your MS Word resume, required compensation, contact information, and availability. One of our managers will contact you to discuss the position in full detail.