Memory Controller Architect
7 days ago
**About the Role**
We are seeking a highly skilled Principal Logic Engineer with expertise in high-performance DRAM memory controllers and DDR4/5 PHYs to join our team at Microsoft Corporation. The ideal candidate will have 8+ years of experience with Double Data Rate 4 (DDR4) or Double Data Rate 5 (DDR5) DRAM Memory Controller design, knowledge of Joint Electron Device Engineering Council (JEDEC) DDR5 Specification, and fluency in Verilog and System Verilog.
**Responsibilities and Qualifications**
- Design and implement major blocks of a DRAM Memory Controller using high-quality Verilog Register Transfer Level (RTL) code.
- Interface with PHY vendors and collaborate with front-end design and physical design teams to ensure correctness of the Micro Controller (MC) design.
- Implement additional required functional units in Verilog and ensure high quality of the design from perspectives of functionality, timing, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Logic Equivalence Check (LEC).
- 9+ years of related technical engineering experience, or equivalent combination of education and experience.
- Knowledge of Joint Electron Device Engineering Council (JEDEC) DDR5 Specification.
**Benefits**
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay.
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