DRAM Memory Design Specialist
5 days ago
We are seeking a skilled Cloud Infrastructure Hardware Engineer Leader to join our team at Microsoft.
As a member of SCHIE, you will play a critical role in shaping the future of cloud infrastructure and hardware engineering, delivering core infrastructure and foundational technologies for our over 200 online businesses, including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform.
Our goal is to empower every person and organization on the planet to achieve more by delivering a trusted experience to customers and partners worldwide, prioritizing smart growth and high efficiency.
This position requires designing and implementing major blocks of a DRAM Memory Controller in Verilog Register Transfer Level (RTL) and ensuring their correctness from various perspectives.
Key Responsibilities- Design and implement major blocks of a DRAM Memory Controller in Verilog RTL.
- Interface with PHY vendors to ensure seamless collaboration.
- Work closely with front-end design and physical design teams to guarantee the correctness of the Micro Controller (MC) design.
- Implement additional required functional units in Verilog as needed.
- Ensure high quality of the design from the perspectives of functionality, timing, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Logic Equivalence Check (LEC).
- A minimum of 9 years of related technical engineering experience.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with 6+ years of technical engineering experience or internship experience.
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with 4+ years of technical engineering experience or internship experience.
- Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with 3+ years of technical engineering experience.
- 8+ years of experience with Double Data Rate 4 (DDR4) or Double Data Rate 5 (DDR5) Dynamic Random-Access Memory (DRAM) Memory Controller design.
- In-depth knowledge of Joint Electron Device Engineering Council (JEDEC) DDR5 Specification.
- Proficiency in Verilog and System Verilog, Dynamic Random-Access Memory Physical Layer (DRAM PHY), Interface Protocol (DFI), and high-speed digital design experience.
This position requires meeting Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
The estimated salary for this role is $226,100 per year in the United States.
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