Principal Physical Design Engineer

3 days ago

Santa Clara, California, United States Astera Labs Full time
Astera Labs Principal Physical Design Engineer

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at

As an Astera Labs Principal Physical Design Engineer, you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.

Key Responsibilities:

  • Support the development of complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Collaborate with designers, verification engineering, and engineering operations to ensure timely and successful product delivery.
  • Develop and maintain timing constraints, timing signoff methodology, and timing closure at the block and full-chip level.
  • Work with Cadence and/or Synopsys physical design tools/flows to drive multiple complex designs to production.
  • Ensure good scripting skills in tcl, python, or Perl.
Requirements:
  • Strong academic and technical background in electrical engineering.
  • ≥10 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude.
Preferred Qualifications:
  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
  • Familiarity with DFT test coverage and debug.
  • Familiarity with ECO methodologies and tools.
Compensation:

The base salary range for this position is USD 160,000.00 to USD 240,000.00, determined based on location, experience, and comparable employee salaries.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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