ASIC Design Verification Engineer Intern

2 weeks ago


Austin, Texas, United States Amazon Full time
About the Role

We are seeking a highly motivated and talented ASIC Design Verification Engineer Intern to join our team at Annapurna Labs, a leading provider of hardware co-design solutions. As a member of our team, you will have the opportunity to work on cutting-edge projects that are shaping the future of machine learning acceleration and FPGA acceleration.

Responsibilities
  • Develop a deep understanding of end customer requirements, including software applications, use models, system architecture, and SoC architecture/micro-architecture solutions.
  • Participate in logic design activities as part of Amazon's machine learning custom silicon solutions.
  • Develop and execute design automation mechanisms and flows.
  • Work with physical design teams to achieve performance and area requirements.
Mentorship & Career Growth

Our team is dedicated to supporting new team members in an environment that celebrates knowledge sharing and mentorship. Projects and tasks are assigned in a way that leverages your strengths and helps you further develop your skillset.

Inclusive Team Culture

We are committed to furthering our culture of inclusion. We have ten employee-led affinity groups, reaching 40,000 employees in over 190 chapters globally. We have innovative benefit offerings, and host annual and ongoing learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences.

Work/Life Harmony

We believe striking the right balance between your personal and professional life is critical to life-long happiness and fulfillment. We offer flexibility and encourage you to find your own balance between your work and personal lives.

Basic Qualifications
  • Enrolled in a Bachelors' degree program or higher in Electrical Engineering, Computer Engineering, or a related field with a graduation conferral date between December 2025 and September 2026.
  • Programming experience in System Verilog or UVM.
Preferred Qualifications
  • Enrolled in a Master's degree program in Electrical Engineering or Computer Engineering.
  • Experience implementing computer architecture concepts and testing Verilog designs.
  • Proficiency with a scripting language (Python or Perl).
  • Experience testing Verilog designs.


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