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Senior ASIC Engineer

1 month ago


Cupertino, California, United States Apple Full time

Role Summary

Apple is seeking a highly skilled Senior ASIC Engineer to join our team in Cupertino. As a key member of our hardware design team, you will be responsible for developing and maintaining methodologies and flows related to timing verification and closure.

Key Responsibilities

  • Develop and maintain timing closure methodologies and flows
  • Generate block and full chip timing constraints
  • Work closely with multi-functional teams to resolve complex timing issues
  • Collaborate with SOC teams to execute design and integration tasks

Requirements

  • Detailed knowledge of ASIC design timing closure flow and methodology
  • Experience in ASIC timing constraints generation and timing closure
  • Expertise in STA tools (Primetime) and flow
  • Knowledge of timing corners/modes, process variations, and signal integrity related issues

Preferred Qualifications

  • Familiarity with synthesis, logic equivalence, DFT, and backend related methodology and tools
  • Experience in timing closure of various test modes such as scan shift, scan capture, at-speed, and BIST testing

About Apple

At Apple, we're committed to innovation and excellence in everything we do. We're looking for talented individuals who share our passion for creating groundbreaking products and services that delight our customers.