Senior Principal Design Verification Engineer

1 week ago

San Jose, California, United States BAE Systems USA Full time

**Job Summary**

We are seeking a highly skilled Senior Principal Design Verification Engineer to join our team at BAE Systems USA. As a key member of our Imaging Solutions organization, you will be responsible for architecting and implementing digital functions of sensors and validating products through programming bring-up systems to achieve world-class performance.

The ideal candidate will have a solid understanding of verification methodologies, especially UVM (SystemVerilog (SV)), including test planning, test bench creation, code and functional coverage, directed and random stimulus generation, assertions, regression triage, and defining detailed test plans and implementing Verilog simulation test cases to verify design functionality.

Additionally, the successful candidate will have experience building verification environments using SV/UVM methodology, building reusable bus functional models, monitors, checkers, and scoreboards, debugging products, testing, and resolving design issues, and integrating VIP cores, buses, controllers, PHYs, etc., with other logic within ASIC/FPGA.

This role involves a combination of collaborative/in-person and independent work, and will take the form of a hybrid work format, with time split between working onsite and remotely.

**Requirements**

Typically a BS with 10 years of experience or MS with 8 years of experience. Desired majors Electrical Engineering, Computer Engineering, or Computer Science. Proficient in SystemVerilog (SV) language for ASIC design, and related FPGA. Knowledge of ASIC design flows is highly desirable, and FPGA is a plus. Knowledge simulation and verification methodologies (Cadence/Synopsys tool simulator, UVM). Excellent organization and communication skills for interacting between different design groups. Proficiency in C/C and scripting languages is a plus.

**Preferred Requirements**

BS in EE or Computer Science, MS or Doctoral degree preferred. 10 years of experience in ASIC/FPGA Development (Verilog, System Verilog, UVM).

**Benefits**

Full-Time Salary Range: $250,400. Employee benefits include health, dental, and vision insurance, health savings accounts, a 401(k) savings plan, disability coverage, and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave.

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