Digital Logic Design and Verification Expert
17 hours ago
**Transform the Future of Electronics with Siemens Digital Industries Software**
Join our team as a Digital Logic Design and Verification Expert and contribute to the development of innovative electronic products that shape the world we live in.
About the Role:
You will play a critical role in the design and implementation of HDL-based verification environments, utilizing your expertise in UVM/OVM/AVM verification methodology, VHDL and/or Verilog HDL simulation, SystemVerilog, Specman/e, Vera, and/or PSL and Assertion-Based Verification techniques.
Key Responsibilities:
- Develop and validate digital logic designs for ASICs and/or FPGAs
- Assist in the implementation of UVM/OVM/AVM verification methodology
- Leverage expertise in VHDL and/or Verilog HDL simulation
- Utilize SystemVerilog, Specman/e, Vera, and/or PSL and Assertion-Based Verification techniques
Requirements:
- Bachelor or Master's degree in Electrical or Computer Engineering
- Newer college graduate (June 2019 - May 2021)
- Coursework/project experience and programming skills in C/C++, Tcl/TK, PERL
- Good understanding of object-oriented concepts as applied to a Verification Environment
- Coursework/experience with HDL-based, register-transfer-level (RTL), digital logic design, verification languages, and functional verification methodology for ASICs and/or FPGAs
Why Siemens?
As a leader in the Electronic Design Automation software industry, Siemens offers a dynamic work environment, cutting-edge technologies, and opportunities for career growth and development. Our benefits package includes competitive compensation, flexible work arrangements, and access to top-notch resources and tools.
Estimated Salary: $45,000 - $68,000 per year, depending on location and qualifications
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