DFT Engineer

5 days ago


Irvine, California, United States Ethan Alexander Group, Inc. Full time
About the Role

We are seeking a highly skilled DFT Engineer to join our team at Ethan Alexander Group, Inc. as a key member of our Test Engineering department. The successful candidate will be responsible for designing and implementing robust test solutions for our mixed-signal SoC products.

Key Responsibilities
  • Design and Implementation
    • Develop and document DFT requirements and specifications for IP, block, and chip-level designs.
    • Execute DFT lint to identify scan DRC violations and resolve them.
    • Implement top-level and hard macro block-level scan insertion with high EDT compression ratios using hybrid LBIST, EDT IP/ATPG, LPCT EDT, and AC scan verification with high-speed PLL, MBIST, and IJTAG.
    • Plan and insert MBIST and memory repair (BISR) at RTL.
  • Pattern Generation and Verification
    • Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests.
    • Verify ATPG patterns on pre- and post-route gate-level netlists, including 0-delay and SDF.
  • Collaboration and Support
    • Work with the backend team to generate MBIST/scan mode constraints, scan reorder, and VCDs for IR drop analysis during DFT, ECO changes, and formal verification (LEC).
    • Support test engineers with pattern generation, tester debug, and failure analysis.
    • Collaborate with the Test Engineering team during silicon bring-up and create flows/scripts necessary for debugging/diagnosing compression LPC ATPG patterns (stuck-at/at speed), MBIST patterns on ATE for development and production programs.
  • Expertise and Tools
    • Expert knowledge of Mentor Tessent toolchain.
    • Hands-on hierarchical DFT flow experience from RTL to netlist.
    • Strong knowledge and experience with both JTAG (IEEE1149.1) and IJTAG (1687).
    • Experience in inserting EDT, wrapper cells, and OCC.
    • Experience in analyzing DFT DRC violations and fault coverage analysis.
    • Expertise in ATPG, debug, and resolving ATPG DRC and chain trace issues.
    • Gate-level simulations and debug, both 0-delay and with SDF DFT.
    • Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation.
    • Experience in debugging tester/ATE failures, silicon bring-up, and yield and test time improvement.
    • Experience in Perl/TCL scripting and good verbal/written communication skills.
  • Requirements
    • 7+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success.


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