Senior Validation Engineer

2 days ago


Santa Clara, California, United States Larsen & Toubro Full time
Job Description & Skill Requirement:

At Larsen & Toubro, we are seeking a highly skilled Post Silicon Validation Engineer to join our team. The ideal candidate will have expertise in validating PCIe, LPDDR controller/chips, and Ethernet interfaces for leading edge protocols, including DRAM functionality related to configuration, tuning, and debugging.

Key Responsibilities:

  • Validate PCIe, LPDDR controller/chips, and Ethernet interfaces for leading edge protocols.
  • Experience in validating PCIe gen4/5 TX/RX and Ethernet interface validation and bring up.
  • Understanding of JEDEC, PCIe Standard, and LPDDR5.
  • Configuration and tweaking of registers during bring up and validation.
  • Validating all features of DDR memory.
  • Validating different Ethernet configurations.
  • Performance measurement of PCIe lanes.
  • Using system debug and handling defects.
  • Experience in handling debug tools, defect management, and repo management system is an added advantage.

Requirements:

  • Expertise in Post silicon validation bring up and validation of interfaces.
  • Experience in validating PCIe, LPDDR controller/chips, and Ethernet interfaces.
  • Understanding of JEDEC, PCIe Standard, and LPDDR5.
  • PCIe gen4/5 TX/RX validation experience is a must have skill.
  • Ethernet interface validation and bring up is a must have skill.


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