Timing Design Engineer
3 weeks ago
At Apple, we're pushing the boundaries of innovation and technology. We're seeking a highly skilled Timing Design Engineer to join our team and contribute to the development of cutting-edge products that delight and inspire our customers.
Key Responsibilities:
- Design and develop high-performance PHY designs from RTL to GDSII
- Generate block-level static timing constraints and close timing on critical blocks
- Develop and validate low-power clock network guidelines
- Perform timing optimization and validation
- Implement ECOs to fix timing issues
- Run timing verification flows and provide guidelines for design fixes
Requirements:
- BS degree in a technical discipline with a minimum of 3 years of relevant experience
- Relevant knowledge of industry standards and practices in timing closures and physical design
- Experience with physically aware synthesis, floor-planning, and place-and-route tools
- Strong understanding of timing flows, physical construction, integration, and physical verification
- Working knowledge of SoC architecture and HDL languages like Verilog
- Power user of industry-standard timing, physical design, and synthesis tools
- Solid understanding of scripting languages like Perl/Tcl
What We Offer:
- Competitive base pay range of $135,400 to $250,600
- Discretionary employee stock programs and stock purchase plans
- Comprehensive medical and dental coverage
- Retirement benefits
- Discounted products and services
- Reimbursement for educational expenses
Apple is an Equal Opportunity Employer:
We're committed to creating an inclusive and diverse workplace where everyone has the opportunity to thrive. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.
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