Senior Physical Design Engineer, Hardware Compute Group

1 week ago

Portland, Oregon, United States Amazon Full time
About the Role

We are seeking a highly skilled Senior Physical Design Engineer to join our Hardware Compute Group team at Amazon. As a key member of our team, you will be responsible for designing and developing innovative hardware solutions that power our cutting-edge products.

Key Responsibilities
  • Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level.
  • Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.
  • Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals.
  • Contribute to developing physical design methodologies.
  • Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams.
Requirements
  • BS in EE/CS
  • 7+ years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm
  • Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
  • Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation.
Preferred Qualifications
  • MS or PhD degree in Computer Engineering/Electrical Engineering or related field
  • Excellent communication and analytical skills
  • Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
  • 7+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain
  • Thorough knowledge of device physics, custom/semi-custom implementation techniques
  • Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc.
  • Experience in extraction of design parameters, QOR metrics, and analyzing trends
  • Experience with DFT & DFM flows
  • Ability to provide mentorship, guidance to junior engineers and be a very effective team player

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