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Physical Design Engineer

2 months ago

Mountain View, California, United States Acceler8 Talent Full time
Acceler8 Talent: Seeking a HW Acceleration Expert

We are looking for an experienced Physical Design Engineer to join our HW acceleration start-up, developing a novel interconnect architecture to eliminate congestion in distributed systems.

Key Responsibilities:
  • Evaluate tool flow for physical implementation in a cloud-first environment.
  • Work on chip-level floorplan and block partitioning, evaluating tradeoffs in interface complexity, block size, and functional partitioning.
  • Define and construct major physical structures, including clock architecture, power delivery network, and interconnect topologies.
  • Establish the P+R workflow at block & chip levels, working with large and complex designs in the latest process technology nodes.
  • Execute block and top-level physical implementation, from floorplan & power plan, through P+R & timing closure.
Requirements:
  • 10+ years' experience in the physical implementation of network switching/routing silicon, such as SmartNICs, PCIe, DPUs, high-speed serial interfaces, etc.
  • Track record of execution on shipped products.
  • Experience working on the latest advanced nodes.
  • Expertise in SystemVerilog and experience with Python, Perl, or other scripting language.
  • Deep experience with the latest CAD tools.
  • Familiarity with a variety of analysis tools.
  • Full chip or top-level integration floorplanning.

We offer a competitive salary of up to $250k base + equity. If you are interested in this opportunity, please apply through our website or contact us for more information.