Timing Design Engineer

2 weeks ago


Beaverton, Oregon, United States Apple Full time
Job Summary

We are seeking a highly skilled Timing Design Engineer to join our team at Apple. As a member of our multifaceted group, you will have the opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every day.

Key Responsibilities
  • Generate block level static timing constraints
  • Closely collaborate with RTL, PD teams to close timing on critical blocks
  • Develop and validate high performance low power clock network guidelines
  • Perform Timing optimization and implement the design for functionality
  • Run Timing verification flow at chip/block level and provide guidelines to fix violations to other designers
Requirements
  • BS degree in technical discipline with minimum 10 years of relevant experience
  • Deep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
  • Confirmed knowledge of Basic SoC Architecture and HDL languages like Verilog
  • Experienced user of industry standard Timing, Physical Design and Synthesis tools
About Apple

Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.



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