Digital Test Development Engineer

2 days ago


Centennial, Colorado, United States SEAKR Engineering Full time

Job Description

The Verification Engineer will be responsible for developing verification and simulation strategies, creating a digital test plan, and providing coverage metrics. This role requires expertise in System Verilog with UVM (Universal Verification Methodology) and experience in regression testing for designs under test. The candidate must be able to extract and derive test requirements and sequences based on design documentation and requirements.

  • Architect and construct full test environments using UVM, including coverage.
  • Analyze and write System Verilog code.
  • Diagnose sophisticated test failures and file results.
  • Analyze code coverage to adjust agent sequence behavior.
  • Diagnose VHDL RTL issues.
  • Perform and evaluate regression tests for designs under test.
  • Use simulation tools like Mentor Graphics Modelsim/Questasim for simulation debug and reporting.


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