Senior ASIC Design Engineer

2 weeks ago


Santa Clara, California, United States Apple Full time
About the Role

At Apple, we're pushing the boundaries of innovation in mobile computing with our cutting-edge SOC's. As a key member of our SoC Design team, you'll play a crucial role in creating the architecture and design for the on-chip system interconnect bus for next-generation Apple SOC's.

Key Responsibilities
  • Analyze architectural requirements of next-generation on-chip fabric and define scalable interconnect components
  • Design and implement high-quality RTL, with embedded assertions and cover points
  • Develop detailed micro-architectural specifications
  • Collaborate with cross-functional teams to define and implement logic IP
  • Work closely with design verification and formal verification teams to debug and verify functionality and performance
Requirements
  • Extensive experience in front-end ASIC RTL digital logic design using Verilog or System Verilog
  • Tight-knit collaboration skills with excellent written and verbal communication skills
  • Familiarity with multiple power domains, multiple clock domains, and asynchronous interfaces
  • Strong understanding of flow control, arbitration, on-chip interconnects, QoS, topology, and performance analysis
  • Experience with implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, logic equivalence checks
What We Offer

At Apple, we offer a comprehensive compensation package, including base pay, discretionary bonuses, and commission payments. You'll also receive benefits such as comprehensive medical and dental coverage, retirement benefits, and a range of discounted products and free services. Additionally, you'll have the opportunity to become an Apple shareholder through our discretionary employee stock programs.



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