RTL Design Validation Engineer

7 days ago


Bellevue, Washington, United States TriOptus LLC Full time

**Job Description:**

We are seeking a Design Verification Engineer to join our team at TriOptus LLC. The ideal candidate will have expertise in developing and implementing comprehensive testbenches in SystemVerilog to validate RTL module functionality.

**Responsibilities:

  1. Plan, develop, and implement testbenches in SystemVerilog.
  2. Execute testbenches consistently, identifying and documenting potential issues and bugs discovered during simulation.
  3. Perform RTL simulations using tools like ModelSim or QuestaSim.
  4. Interpret and analyze state machine and module implementations from RTL code.
  5. Utilize shellbash scripting to automate test execution.
  6. Conduct detailed RTL code reviews.

**Requirements:

  • Hold a Professional Engineer certification.
  • Meet the basic qualification requirements.
  • Possess additional skills such as design engineering.

**Salary and Benefits:**

The estimated salary for this position is $120,000 - $150,000 per annum, based on location and experience. No background check or drug screening is required.



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