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Senior Hardware Design Engineer

2 months ago

Palo Alto, California, United States InDepth Engineering Solutions Full time
Job Description

At InDepth Engineering Solutions, we are seeking a highly skilled Sr. Physical Design Engineer to join our team. As a key member of our design team, you will be responsible for contributing to all design phases of physical design of high-performance SoC design at both the block and subchip levels, as well as the full-chip level from RTL to GDSII.

Responsibilities:
  • Collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power Integrity teams to drive the overall Physical Design aspects, leading to a successful tapeout and production silicon.
  • Perform subchip level and block level place and route, and close design to meeting performance, power and area.
  • Lead and Perform all aspects of full chip SoC integration activities: die size optimization, floorplanning, hard IP integration, partitioning, chip level clock planning, bump placement / RDL routing, power grid generation, full chip STA timing, DFT strategy planning, and final physical verification.
  • Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) on-die model for package & die co-design analysis.
  • Define EM-IR signoff requirements and sign-off methodology.
  • Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis.
Requirements:
  • Extensive physical design experiences at both the block level and subchip level, as well as full-chip level is a plus.
  • Deep knowledge in physical design, including physical aware synthesis, floorplanning, clock tree implementation, routing, STA timing signoff, and chip-finishing.
  • Good knowledge of basic soc architecture. Be able to work with Front-end design team to address timing, congestion and power issues.
  • In-Depth Knowledge of design flow from RTL to GDSII.
  • Good knowledge of EM-IR sign-off requirements.
  • Experience in using EDA tools like Synopsys (/Cadence) for PPA optimization.
  • Good script skills such as perl/tcl.