Embedded Systems Design Lead

1 week ago


San Diego, California, United States Cisco Systems, Inc. Full time

Salary: $140,000 - $200,000 per annum

Cisco Systems, Inc. is a global leader in networking and cybersecurity solutions. Our Common Hardware Group (CHG) designs the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products.

We are seeking an experienced Embedded Systems Design Lead with expertise in Design-for-Test (DFT) to join our Silicon One development organization in San Jose, CA. As an ASIC Implementation Technical Lead, you will work closely with Front-end RTL teams and backend physical design teams to drive DFT requirements early in the design cycle.

About the Role:

  • You will be responsible for implementing hardware DFT features that support ATE, in-system test, debug, and diagnostics needs of the designs.
  • Develop innovative DFT IP in collaboration with multi-functional teams and play a key role in full-chip design integration with testability features coordinated in the RTL.
  • Work closely with design/design-verification and PD teams to enable integration and validation of Test logic in all phases of the implementation and post-silicon validation flows.

Requirements:

  • Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 6 years of experience.
  • Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
  • Familiarity with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
  • Experience working with Gate level simulation, debugging with VCS and other simulators.
  • Prior experience with Post-silicon validation and debug; Ability to work with ATE patterns, P1687.
  • Scripting skills: Tcl, Python/Perl.

Preferred Qualifications:

  • Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification.
  • DFT CAD development – Test Architecture, Methodology and Infrastructure.
  • Background in Test Static Timing Analysis.
  • Past experience with Post-silicon validation using DFT patterns.


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