Physical Design Power Integrity Flow Development Engineer

1 week ago


Phoenix, United States Experis Full time

Job Title: Physical Design-Power Integrity Flow Development Engineer

Location:


Primary: Phoenix, AZ
Secondary: Remote in the US.


Experience Level: L2 (3-7 years)
Work Authorization: USC or GC preferred.

Job Description:


Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design at various design stages, from RTL to gate-level netlist.
Develop and own power grid implementation for multi-hierarchy low power designs, including power analysis, IR Drop, EM, and IR drop-based STA in advanced technology nodes (5nm and below).
Resolve power and power integrity issues related to physical design, identify potential low-power solutions, and drive execution and methodology improvements.


Qualifications & Requirements:

Basic Qualifications:


Bachelor's degree in Electrical Engineering or Computer Science.
5 - 9 years of experience in:

RTL2GDSII design flow usage & development in advanced technology nodes (7nm and below)
Low power implementation and signoff, including power gating, multiple voltage rails, and UPF/CPF usage
Power grid design & implementation
Power integrity analysis at block and top level, including EM, IR & ESD analysis, and power reduction techniques in SOC design
Power constraints generation and validation, power analysis, and interfacing with power integrity analysis tools such as thermal analysis
Strong expertise in Python & TCL programming
EDA tools, including Redhawk/Voltus, DesignCompiler/Genus, Primetime/PrimePower/Joules, FusionCompiler/ICC2/Innovus




Preferred Qualifications:


Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.
Knowledge of static timing analysis, low power concepts, defining timing and power constraints exceptions, switching activity definitions, and simulation vectors generation & usage.



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