Design Verification Engineer

1 week ago


Bellevue, United States JobRialto Full time
Job Summary:

The Design Verification Engineer will be responsible for validating RTL module functionality and ensuring design accuracy across various scenarios. This role requires expertise in developing and executing testbenches in System Verilog, performing RTL simulations, and utilizing scripting for automation. The engineer will also contribute to design reviews and collaborate with cross-functional teams to enhance design quality.

Key Responsibilities:

• Plan, develop, and implement comprehensive testbenches in System Verilog to validate RTL module functionality across various scenarios.

• Execute testbenches consistently, identifying and documenting potential issues and bugs discovered during simulation.

• Perform RTL simulations using tools like ModelSim or QuestaSim to verify design accuracy and troubleshoot errors.

• Interpret and analyze state machine and module implementations from RTL code to identify various scenarios for targeted testing.

• Utilize shell/bash scripting to streamline and automate the test execution process, enhancing workflow efficiency.

• Conduct detailed RTL code reviews in alignment with model diagrams, offering constructive feedback to improve design fidelity.

• Actively participate in design review meetings, contributing insights and recommendations to ensure robust design architecture.

Required Skills and Qualifications:

• 3-4 years of experience in RTL coding and design verification.

• Strong proficiency in System Verilog for testbench development.

• Experience with RTL simulation tools such as ModelSim or QuestaSim.

• Proficient in shell/bash scripting for automation.

• Solid understanding of state machine and module implementations from RTL code.

• Experience with detailed RTL code reviews and providing feedback to improve design quality.

• Ability to work collaboratively in design review meetings and offer insights for design improvements.

Preferred Qualifications:

• Experience in complex system designs and verification across various hardware platforms.

• Familiarity with FPGA or ASIC design flows and verification methodologies.

• Knowledge of other hardware description languages (VHDL, Verilog).

Certifications:

• Relevant certifications in digital design or verification (e.g., SystemVerilog, UVM) are a plus.

Education: Bachelors Degree

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