SOC Verification Engineer

About HCLTech: HCLTech is a global technology company, home to 221,000+ people across 60 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services,...

About HCLTech:HCLTech is a global technology company, home to 221,000+ people across 60 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services,...

About HCLTech:HCLTech is a global technology company, home to 221,000+ people across 60 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services,...

Required Qualifications 4+ years' experience required in verification. System Verilog /UVM experience (Mandatory). Good understanding of PCIe and Ethernet is needed. Engineer must have good understanding of complete verification life cycle (test plan test bench till coverage closure). Define SoC verification strategy. Good understanding of SoC life cycle....

Required Qualifications 4+ years' experience required in verification. System Verilog /UVM experience (Mandatory). Good understanding of PCIe and Ethernet is needed. Engineer must have good understanding of complete verification life cycle (test plan test bench till coverage closure). Define SoC verification strategy. Good understanding of SoC life cycle....

Looking to add DV Engineers in Irvine, San Diego and Santa Clara. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System...

Role: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: Mandatory JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Role: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: Mandatory JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans...

Role: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: Mandatory JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans...

We are now looking for a Senior Verification Engineer for our Tegra group NVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multi-layered and dynamic, technology-focused company impacting product lines...

Role: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: MandatoryJOB DESCRIPTION:Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. Develop test plans and...

JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans and coverage metrics from specifications and writing block and chip-level tests. • Create PERL/Python scripts to...