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Design Verification Engineer

4 months ago

Santa Clara, United States Mirafra Technologies Full time

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.

On going needs additional 10 engineers in team.

Position detail: SOC verification

Experience level : 5-20 years

Architect block and full-chip verification environments using HVLs and constrained random

techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA

Develop test plans and coverage metrics from specifications and write block and chip-level

tests in C,SV,UVM

Debug RTL and Gate simulations and work with design engineers to verify fixes.

Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.

Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.

Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.

Evaluate latest verification methodologies and develop scripts etc. to automate verification

flows.