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Staff SoC Performance Engineer
3 months ago
Job Description
Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC. The collection of silicon proven interconnects, security IP, system controllers, debug and trace and IP tooling are all designed, validated and optimized to be used with Arm Cortex processors and Arm Mali Multimedia IP. Drive the open AMBA interface standard, System IP provides design teams with the foundation for building better systems.
Job Description:
We are looking for experienced SoC performance engineers who are passionate about enhancing system performance on Arm IPs. This role will involve collaborating with a brilliant team of architects and performance engineers in driving the development of new high-performance interconnect IPs. Your contributions will help in optimizing Arm systems in the infrastructure, automotive, and mobile space. You will apply your performance analysis skills in modeling and evaluating new features for future IPs, and will play a key role in productizing performance models for partners in the Arm ecosystem.
Responsibilities:
Collaborate with micro-architects and validation engineers to develop cycle-accurate timing models, and drive new feature development for coherent and non-coherent interconnects.
Develop a high quality, correlated model for customer evaluation and internal analysis.
Work closely with internal and external teams, delivering the collateral needed to develop the highest performing systems based on Arm technology.
Validate performance expectations on the IP by designing test suites, identify performance bottlenecks and propose solutions.
Required Skills and Experience:
Minimum Bachelor's Degree in Electrical Engineering, Computer Engineering or Computer Science with a strong background in computer architecture, microarchitecture, and performance analysis.
Minimum of 4 years of experience within the SoC Performance Modeling, RTL in the semiconductor industry.
Consistent track record in developing cycle accurate performance models, and evaluating microarchitectural features for performance improvements in future interconnects.
Proficient in C++ for programming for large-scale software development, familiarity with SystemC TLM, and Python scripting
skills.
Nice to haves:
Knowledge of interconnect micro-architecture design, PCIe and CHI protocols.
Understanding of workloads used for performance optimization.
Experience with performance verification methodologies, and correlating software models to RTL.
In Return:
We offer a hybrid approach to home and office working to provide an adaptable experience for all employees. We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodating to different home working requirements.
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