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Senior ASIC Verification and Infrastructure Engineer

3 months ago


Santa Clara, United States TWIN OAKS ASSISTED LIVING AND MEMORY CARE Full time

NVIDIA is seeking outstanding Senior Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO engineering teams. This position offers the opportunity to have a big impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to artificial intelligence to self-driving cars and supercomputers. Our DV infrastructure and methodology team automates, analyzes, and optimizes the verification and deployment of next-generation hardware and firmware designs throughout Nvidia. What you’ll be doing: Improve the speed, flexibility, and extensibility of the High-Speed IO front end integration, build, and verification flows

Apply best in class internal and industry tools to enable flows that simplify work processes

Find out needs of the team and create solutions; explain to the team how to maximize productivity with the tools you provide

Keep the High-Speed IO Continuous Integration system at the cutting edge of industry techniques

Collaborate with architects, designers, verification engineers, as well as methodology and infrastructure engineers to accomplish your tasks

Deploy tracking metrics to resolve operational issues, drive forecasting, and improve design productivity

Remove inefficiency wherever you can find it

What we need to see: Bachelors or Masters in Computer Science, Computer Engineering, Electrical Engineering or closely related degree (or equivalent experience)

5+ years of relevant industry experience

Exposure to computer architecture, ASIC design, and verification methodology is required

Experience with verification methodology (UVM or similar)

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi interactive, Debussy, GDB)

Programming proficiency in Python, Perl, or other Systems Programming language

Fluency in Object Oriented Programming with SystemVerilog

Experience with Make based build systems in large, distributed computing environments

Experience with Continuous Integration pipelines

You should display a tenacity to root cause and fix Infrastructure problems, especially intermittent, hard to isolate issues in a complex computing environment

Strong problem-solving, debugging and analytical skills

Good interpersonal skills and ability & desire to work as a great teammate

A drive for automating processes and creating solutions that are easily integrated into existing tool flows

Ways to stand out from the crowd: Experience delivering IP to multiple GPUs/SoCs in parallel

Experience creating shareable and maintainable Continuous Integration pipelines in Jenkins

Strong verification mindset and intuition

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working with us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field The base salary range is 128,000 USD - 258,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and

benefits .

NVIDIA accepts applications on an ongoing basis. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr