Current jobs related to Design Verification Engineer - San Jose - CV Library

  • Design Verification Engineer

    3 weeks ago

    San Jose, United States Nexus Semiconductor Recruitment Full time

    We are seeking a talented Design Verification Engineer to join our team. In this role, you will play a critical part in ensuring the quality and reliability of our integrated IP subsystems by developing comprehensive test benches and executing rigorous verification processes. Responsibilities: Develop and maintain test benches using industry-standard...

  • Design Verification Engineer

    3 weeks ago

    San Jose, United States Nexus Semiconductor Recruitment Full time

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  • Design Verification Engineer

    4 weeks ago

    San Jose, United States Nexus Semiconductor Recruitment Full time

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  • Design Verification Engineer

    2 months ago

    San Jose, United States Quest Global Full time

    Quest Global is hiring for design verification engineer job position in the location of San Jose,CA. Below are the details. If interested please share your resume at shashank.verma@quest-global.com.Title :: Design Verification Engineer Location :: San Jose,CAJob description:Looking for an experienced verification engineer to participate in following...

  • Design Verification Engineer

    1 month ago

    San Jose, United States Canvendor Full time

    Title : Design Verification EngineerLocation : San Jose , CA / San Diego , CA Employment Type : Long Term ContractSkills and Qualifications:• BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role• Proficient in System Verilog/UVM/OVM, and OOP/C++• Deep understanding of constrained randomization...

  • Design Verification Engineer

    4 weeks ago

    San Jose, United States Canvendor Full time

    Title : Design Verification EngineerLocation : San Jose , CA / San Diego , CA / Austin, TX (3 days per week)Employment Type : Long Term ContractSkills and Qualifications:• BS in Computer Engineering, BSEE or comparable and 6+ years of industry experience in a design verification role• Proficient in System Verilog/UVM/OVM, and OOP/C++• Deep...

  • Design Verification Engineer

    3 months ago

    San Jose, United States Intelliswift Software Full time

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  • Design Verification Engineer

    3 months ago

    San Jose, United States Intelliswift Software Full time

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  • Design Verification Engineer

    3 weeks ago

    San Jose, United States ACL Digital Full time

    Position: Design Verification Engineer Location: San Jose/Austin (Onsite/Hybrid) Position Overview: 5+ years of relevant experience in Design Verification. Experience with System Verilog and UVM is a must. Strong experience in testbench development such as UVM methodology. Knowledge of GPU, experience with Shader, Texture, or Memory System a...

  • Design Verification Engineer

    1 month ago

    San Jose, United States Mastech Digital Full time

    Job Title: DV Engineer (GPU)Long Term ContractLocation : Hybrid onsite 3 days per week (No Remote candidate)Job DescriptionKnowledge of Block-level (unit level)Debugging and developmentUVM, System Verilog exp8 to 10 years of hands-on related expAs a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture....

  • Design Verification Engineer

    2 months ago

    San Jose, United States Mastech Digital Full time

    Job Title: DV Engineer (GPU)Long Term ContractLocation : Hybrid onsite 3 days per week (No Remote candidate)Job DescriptionKnowledge of Block-level (unit level)Debugging and developmentUVM, System Verilog exp8 to 10 years of hands-on related expAs a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture....

  • Design Verification Engineer

    3 weeks ago

    San Jose, United States Canvendor Full time

    Job Title: Design Verification Engineer Job Location: San Jose, CA(Onsite) Type: Contract Duration: 12+ Months Job Description: Triage regression failures and make testbench updates. Debug functional errors in RTL model using simulation and debug tools. Maintain efficient and clean regression status. Develop Scalable System Verilog/UVM testbenches for unit...

  • Lead Design Verification Engineer

    3 days ago

    San Jose, California, United States Sql Pager LLC Full time

    Job Title: Lead Design Verification EngineerJob Summary:We are seeking a highly skilled Lead Design Verification Engineer to join our team at Sql Pager LLC. As a key member of our engineering team, you will be responsible for leading the design verification efforts on complex semiconductor products.Key Responsibilities:Lead the verification efforts on PCIe...

  • ASIC Design Verification Engineer

    6 days ago

    San Jose, California, United States Broadcom Corporation Full time

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  • Design Verification Engineer

    2 months ago

    San Jose, United States ACL Digital Full time

    Position: Design Verification EngineerLocation: San Jose/Austin (Onsite/Hybrid)Position Overview:5+ years of relevant experience in Design Verification.Experience with System Verilog and UVM is a must.Strong experience in testbench development such as UVM methodology.Knowledge of GPU, experience with Shader, Texture, or Memory System a...

  • AI Design Verification Engineer

    1 month ago

    San Jose, United States CV Library Full time

    Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...

  • Design Verification Engineer

    4 weeks ago

    San Jose, United States Canvendor Full time

    Job Title: Design Verification EngineerJob Location: San Jose, CA(Onsite)Type: ContractDuration: 12+ MonthsJob Description:Triage regression failures and make testbench updates.Debug functional errors in RTL model using simulation and debug tools.Maintain efficient and clean regression status.Develop Scalable System Verilog/UVM testbenches for unit level...

  • Staff Engineer, Design Verification

    1 month ago

    San Jose, United States GreenWave™ Radios Full time

    Job DescriptionJob DescriptionInnoPhase Inc., DBA GreenWave™ Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active...

  • Staff Engineer, Design Verification

    2 months ago

    San Jose, United States GreenWave™ Radios Full time

    Job DescriptionJob DescriptionInnoPhase Inc., DBA GreenWave™ Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active...

  • Asic Design Verification Engineer

    2 months ago

    San Jose, United States Broadcom Corporation Full time

    Job Description: You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed...

Design Verification Engineer

1 month ago

San Jose, United States CV Library Full time

LeadStack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world. Title: Design Verification Engineer Location: San Jose CA - Hybrid Duration: 12 Months Job Description: As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Note: Current state-of-the-art testbench development such as UVM methodology Experience in design verification with UVM and SystemVerilog is a MUST Responsibilities: Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug tools. Maintain efficient and clean regression status Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification. Review Architecture and Micro-Architecture specifications. Closely work with Architects and RTL designers. Define, maintain and execute unit level and/or Cluster level verification testplans. Generate and run Testcases on logic simulation models. Code Functional coverage models and System Verilog assertions. Drive Functional Coverage and Code coverage to closure. Integrate C++ reference model into Scoreboards Requirements: 5-15 year's industry experience in a design verification role. Proficient in System Verilog/UVM/OVM, OOP/C++ Knowledge of GPU, experience with Shader, Texture, or Memory System a plus Experience with code coverage and functional coverage driven verification methodology. Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench. Excellent working knowledge of scripting such as Python or Perl. Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines. Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development. Strong debugging skills Strong programming skills with good understanding of algorithms and data structures Good verbal and written communication skills. If interested, please share your updated resume and the best time and number to connect over the phone. In case you are not available/interested, will appreciate if you can share it with your friends/network. Your referrals are appreciated To know more about current opportunities at LeadStack, please visit us at (url removed) Should you have any questions, feel free to call me on (phone number removed) or send an email on #J-18808-Ljbffr