Staff Engineer, Design Verification
1 month ago
InnoPhase Inc., DBA GreenWave™ Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.
Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.
Are you looking to grow your career at a company that 93% of our current staff approve of our leadership, values, and goals?
To learn more about GreenWave™ Radios, visit the GreenWave™ certification profile at GreatPlacetoWork.com and our website at Home - GreenWave Radios.
As Staff Engineer, Design Verification, you will be the key contributor to the ORAN SoC product design verification team and collaborate with FW & design team for product requirement definition and microarchitecture study. You will participate in the verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You also will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 5+ years of industrial experience to grow their technical career and leadership to climb up corporate ladders and join the exciting cellular product market.
This position will be based in San Diego, Irvine, or San Jose, California.
Key Responsibilities:
- Develop a testbench environment to verify the design at the IP/ Subsystem and SoC Levels using SystemVerilog and UVM.
- Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
- Develop and execute verification plans based on design specifications and collaboration with architects and designers.
- Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases.
- Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW emulation/acceleration, and SW-driven verification.
- Debug test cases and report verification results to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
- Assist in emulation, FPGA, and prototyping efforts.
- Implement and maintain automated verification flows in Python and Perl/ Shell scripts.
Job Requirements
- Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS
- Eight or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off
- Good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
- Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from the scratch
- Proficient in System Verilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell
- Experience in developing IP/ Subsystem/ chip-level System Verilog and UVM based test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and testing
- Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB etc.)
- Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus
- Track record of successfully executing block or chip-level verification plans
- Excellent communication and presentation skills, energetic and self-motivated
- Work effectively with an off-site/ offshore design and verification teams across locations
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